Elapsed time and terminal speed computer for automotive vehicles

ABSTRACT

A speed and elapsed time computer has a digital display in view of the driver of an automotive vehicle. A row of selector switches permits the driver to select one of several modes of operation, including &#39;&#39;&#39;&#39;speedometer,&#39;&#39;&#39;&#39; &#39;&#39;&#39;&#39;terminal speed,&#39;&#39;&#39;&#39; and &#39;&#39;&#39;&#39;elapsed time.&#39;&#39;&#39;&#39; A magnetic pickup senses the rotation of an undriven wheel, and wheel pulses are produced in response to the sensed rotation. In the elapsed time mode, timing signals from a time base oscillator are counted from the time the vehicle leaves a standing start until a number of wheel pulses have been produced corresponding to a predetermined distance, such as a quarter mile. At the end of the run, the elapsed time is displayed; the driver may then operate the terminal speed switch and the speed reached at the end of the quarter is displayed. Speed is computed from the period of a wheel revolution obtained from the wheel pulses, and from the number of pulses produced by the vehicle in traversing a given distance, which may also be a quarter mile. In the speedometer mode, the speed computer operates continuously and its output is continuously displayed. Calibration of the apparatus is readily accomplished by a calibration mode which is also selectable by the operator, in which mode the vehicle is driven over a measured course to determine the number of wheel pulses produced, in order that this characteristic of the particular vehicle may be preset into the computer.

United States Patent [1 1 Stevens et al.

[451 July 24,1973

Inventors: Harry S. Stevens, Kansas City; Jerry W. Karr, Pleasant Hill;Dennis D. Miller, Buckner; Forrest H. Ballinger, Grain Valley, all ofMo.

OTHER PUBLICATIONS J. M. Shulman, Accurate Tachometry Methods withElectronic Counters, Communications and Electronics, November, 1954, pp.452-455.

Primary ExaminerMichael J. Lynch AttorneyD. A. N. Chase A speed andelapsed time computer has a digital display in view of the driver of anautomotive vehicle. A row of selector switches permits the driver toselect one of several modes of operation, including speedometer,terminal speed, and elapsed time. A magnetic pickup senses the rotationof an undriven wheel, and wheel pulses are produced in response to thesensed rotation. In the elapsed time mode, timing signals from a timebase oscillator are counted from the time the vehicle leaves a standingstart until a number of wheel pulses have been produced corresponding toa predetermined distance, such as a quarter mile. At the end of the run,the elapsed time is displayed; the driver may then operate the terminalspeed switch and the speed reached at the end of the quarter isdisplayed. Speed is computed from the period of a wheel revolutionobtained from the wheel pulses, and from the number of pulses producedby the vehicle in traversing a given distance, which may also be aquarter mile. In the speedometer mode, the speed computer operatescontinuously and its output is continuously displayed. Calibration ofthe apparatus is readily accomplished by a calibration mode which isalso selectable by the operator, in which mode the vehicle is drivenover a measured course to determine the number of wheel pulses produced,in order that this characteristic of the particular vehicle may bepreset into the computer.

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ELAPSED TIME AND TERMINAL SPEED COMPUTER FOR AUTOMOTIVE VEHICLES Thisinvention relates to a time and speed computer for automotive vehicles,which is contained within and transported by the vehicle and has adigital display for indicating speed continuously, terminal speed, orelapsed time as selected by the operator.

Heretofore, computations relating to the performance of an automotivevehicle have for the most part been performed by equipment permanentlyinstalled at a track used exclusively for vehicle testing or racing. Theracing enthusiast in particular oftentimes desires accurate timing ofthe performance of his car during trial runs which may be made when thetiming tower of the track is not in operation, or on private tracks orabandoned roads not equipped with any type of timing equipment.Manifestly, corrected speedometers and stop watches may be used and areoftentimes the only means available to measure performance under suchconditions, but these devices are inherently subject to error and areinconvenient to use in drag racing runs, for example, where the driverdesires to give his undivided attention to operation of the vehicle.

It is, therefore, an important object of the present invention toprovide a time and speed computer for automotive vehicles which iscontained within the vehicle itself and which measures the performanceof the vehicle under actual operating conditions without driverattention during a performance run.

Another important object of the invention is to provide a computer asaforesaid capable of various modes of operation including continuousoperation as a speedometer, computation of elapsed time from a standingstart over a measured course, and the computation of terminal speed atthe end of such course.

Still another important object of the invention is to provide an elapsedtime computer in which a train of pulses is produced in response tomovement of the vehicle, the number of such pulses being indicative ofthe distance traveled by the vehicle and the interval between successivepulses being dependent upon the speed of the vehicle, and in whichtiming signals from a time base oscillator are counted from the time thevehicle leaves a standing start until a number of such pulses have beenproduced corresponding to the length of the course.

Yet another object of the invention is to provide a speed computer fordetermining speed continuously or for computing the terminal speed ofthe vehicle at the end of a measured course, wherein the speedcomputation is based on the period of a wheel revolution and the numberof such revolutions required to traverse a given distance.

Furthermore, it is an important object of this invention to provide acomputer as set forth above having a digital display employed toselectively read out either time or speed information, and wherein bothelapsed time and terminal speed information are stored within thecomputer for selective readout by the display after a performance run.

Additionally, it is an important object of the invention to provide sucha computer which may be readily calibrated for a particular vehicle byan unskilled operator without special tools or complex procedures, butwhich nonetheless is highly accurate.

In the drawings:

FIG. 1 is a front perspective view of the computer unit showing thedigital display and the push button selector switches;

FIG. 2 is a side elevational view of a steered, undriven wheel of avehicle showing the pickup device of the present invention;

FIG. 3 is a view of the pickup device itself as seen I from the wheelside thereof;

FIGS. 4a-4b is a schematic and logic diagram of the computer;

FIG. 5 is a block diagram showing a modification of the circuitry ofFIGS. 4a-4b;

FIG. 6 is a block diagram of another modification of the circuitry ofFIGS. 4a-4b;

FIG. 7 is a timing diagram illustrating the operation of the computer inthe terminal speed mode; and

FIG. 8 is a timing diagram illustrating the operation of the computer inthe speedometer mode.

DESCRIPTION FIGS. 1-6

Referring initially to FIG. 1, a housing 10 is shown in which thecomputing apparatus of the present invention is contained, the housing10 being provided with a transparent front panel 12 through which adigital display 14 may be seen. The number displayed in FIG. 1 is 14.85and refers to an elapsed time of 14.85 seconds. A row of push buttonselector switches 16 is located along the bottom of the panel 12 and,from left to right, are labeled OFF, SP" for speedometer mode, T8 forterminal speed mode, ET" for elapsed time mode, CL meaning clear, andRES" meaning reset. The functions of the mode switches and the clear andreset switches will be explained hereinbelow.

Referring to FIGS. 2 and 3, a steered and undriven wheel 18 of avehicle, such as a car modified for drag racing, is shown provided witha pair of diametrically opposed, permanent magnets 20 mounted on itsrim. A pickup device 22 is mounted on the control arm 24 of the wheel18, and includes a pickup coil housed within a cylindrical, nonmagneticcase 26 carried by a mounting plate 28. Straps or other suitablefasteners are employed to attach the mounting plate 28 to the controlarm 24 with the case 26 alignedwith the rim of the wheel 18.Accordingly, as each of the magnets 20 passes the pickup coil, anoscillatory impulse is induced therein as is illustrated in FIG. 4a.

The computer logic is illustrated in FIGS. 4a-4b. A crystal controlled,time base oscillator 30 produces a Hz square wave which is fed to theclock inputs C of a pair of JK flip-flops 32 and 34. The square waveprovides a series of timing signals which, besides controlling theflip-flops 32 and 34, are fed along a lead 36 to one input of a Z-inputNAND gate 38. The flip-flops 32 and 34 are interconnected in a one-shotarrangement, the Q output of the flip-flop 34 being connected to the Kdata input of the flip-flop 32, while the 6 output of the flip-flop 34is connected to the J data input of the flip-flop 32. The K data inputof the flip-flop 34 is maintained at the low logic level (as indicatedby the ground symbol), and the Q output of the flip-flop 32 is connectedto the J input of the flip-flop 34. The output of the arrangement istaken from the Q output of the flip-flop 32, and appears on a lead 40that extends to one input of a 2-input NAND gate 42. A push buttonoperated reset switch 44, upon operation thereof, places the resetinputs of the flip-flops 32 and 34 at the low logic level as indicatedby the reset pulse 46, the

latter being transmitted on to other portions of the circuitry by leads48 and 50. At this juncture, it should be understood that two voltagelevels are employed in the present invention in accordance with binarylogic, and are referred to herein as the low and the high logic levels.

A variable frequency calibration oscillator 52 has a square wave outputwhich is delivered along a lead 54 to the other input of the NAND gate42. A lead 56 connects the lead 54 to one input of a Z-input NAND gate58, thus both of the gates 42 and 58 receive the output from thecalibration oscillator 52. The output of the NAND gate 42 is connectedto one input of another 2- input NAND gate 60, the output thereof beingconnected to the up-counting input of an up/down counter 62. The counter62 is a synchronous counter having a borrow output 64 connected to areset input of a setreset flip-flop 66 comprising a pair of crosscoupled NAND gates and 70. The output of the flip-flop 66 is taken atthe output of the NAND gate 70 and is at the low logic level when theflip-flop is reset. A lead 72 connects this output to the other input ofthe NAND gate 38.

The flip-flop 66 is set by the closing of a mercury switch 74 whichserves as an inertial switch to sense the motion of the vehicle. A highfrequency by-pass condenser 76 is connected across the mercury switch 74to prevent high frequency ignition noise from triggering the flip-flop.It may be noted that the flip-flop 66 and the JK flip-flops 32 and 34,and type D flip-flops and other set-reset flip-flops to be describedhereinafter, are activated by low logic levels at their set and resetinputs.

The NAND gate 38 has its output connected to an elapsed time counter 78.A reset input for the counter 78 is indicated and is connected to thereset lead 48.

The output of the pickup device 22 is fed to a low pass filter 80 forhigh frequency suppression, the output of the filter 80 being connectedto the control input of a Schmitt trigger 82. Accordingly, the output ofthe Schmitt trigger 82 comprises a train of wheel pulses of rectangularform, two pulses occurring for each revolution of the wheel 18. Thispulse train is fed to one input of a 2-input NAND gate 84 and via a lead86 to a normally closed contact of a 3-pole calibration switch 88. Thecircuitry is illustrated in condition for either elapsed time orterminal speed operation, hence the calibration switch 88 is shown inits normal, inoperative position where the wheel pulses are conductedthrough the center pole of the switch 88 to the downcounting input ofthe counter 62. For calibration'purposes, as will be explained, aninverter 90 is connected between the lead 86 and the normally opencontact .of the uppermost pole of the switch 08, such upper pole beingdirectly connected to the second input of the NAND gate 60.

A push button switch 92 identified by the legend CLEAR is connected to areset input of the counter 62 and, upon closure thereof, grounds suchinput at the low logic level to clear the register. A second reset inputis also provided and is connected to the reset lead 48 by a lead 94,thereby also providing for the clearing of the register when the resetswitch 44 is closed.

The lowermost pole of the calibration switch 08 is grounded at the lowlogic level and has a normally open contact connected to one of thereset inputs of a 2- input set, 2-input reset flip-flop 96 comprising apair of cross coupled NAND gates 98 and 100. The output of the flip-flop96 is taken at the output of the NAND gate 100 and is at the low logiclevel when the flip-flop 96 is reset. A lead 102 connects this output tothe reset input of a type D flip-flop 104 and to the set input of a typeD flip-flop 106. The flip-flops 104 and 106 are interconnected in adivide-by-3 configuration.

A single pole switch 108 is identified by the legend SPEED and, uponclosure thereof, places one of the set inputs of the flip-flop 96 at thelow logic level. Simultaneously, via a lead 110, one of the inputs of a3- input NAND gate 112 is placed at the lower logic level. The other setinput of the flip-flop 96 is connected by a lead 1 14 to the output 64of the up/down counter 62. The lead 50 extending from the reset lead 48is connected to the remaining reset input of the flip-flop 96. It shouldbe understood that the SPEED switch 108 is used to place the apparatusin the speedometer mode and corresponds to the SP push button shown inFIG. 1. The CLEAR switch 92 and the RESET switch 44 likewise correspondto the CL and RES push buttons respectively.

The other two inputs of the NAND gate 112 are respectively connected tothe 6 output of flip-flop 104 via lead 116 and the 6 output of theflip-flop 106. The output of the NAND gate 112 is connected to thesecond input of the NAND gate 84, the output thereof being fed to theclock inputs C of the flip-flops 104 and 106. A 2-input NAND gate 114has one of its inputs connected to the 6 output of the flip-flop 106,its other input connected to the Q output of the flip-flop 104, and itsoutput connected to the data input D of the flipflop 104. The data inputD of the flip-flop 106 is connected via lead 116 to the 6 output of theflip-flop 104.

A 3-input NAND gate 118 has one input connected to the Q output of theflip-flop 104, a second input connected to the 6 output of the flip-flop106, and its third input connected to a lead 120 extending from theoutput of the Schmitt trigger 82. The output of the NAND gate 118 is fedto the set input of a set-reset flip-flop 122 comprising a pair of crosscoupled NAND gates 124 and 126. The output of the flip-flop 122 is takenat the output of the NAND gate 126 and is fed to one input of a 2-inputAND gate 128. The other input of the AND gate 128 is connected to the 6output of the flipflop 104 by a lead 130, the output thereof being feddirectly to the activating input of a clock 132 in the computationsection 134 of the computer apparatus. A lead 136 is connected to theoutput of the flip-flop 122 for reset and blanking functions to bediscussed.

The output of the NAND gate 118 is also connected via lead 138 to thepresent input of an augend/sum register 139 in the computation section134. The computation section further includes an up-counter 140responsive to the output of the NAND gate 58, and an adder 142. Theup-counter 140 has a reset input connected by lead 144 to the output ofa 2-input NAND gate 146, the inputs thereof being connected to the 6output of the flip-flop 104 and the lead 120 respectively. A lead 148delivers an end of computation command from the adder 142 to the resetinput of the flipflop 122.

The adder 142 has a quotient output 150 which is connected to thecounting input of a speed register 152. The output of a 2-input NANDgate 154 is connected to the reset input of the register 152. The twoinputs of the NAND gate 154 are respectively connected to the reset lead48 and the lead 138.

A mode switch 156 is schematically illustrated in FIG. 4b and has threesets of switching inputs, the first set receiving the output of theelapsed time counter 78, the second set receiving the output of theup/down counter 62 as indicated by the leader 1.58, and the third setreceiving the output of the speed register 152. Any one of these threesets of inputs is selectively switched to a decoder 160 comprising abinary coded decimal to 7-segment decimal display decoder. Accordingly,the output of the decoder 160 is fed directly to suitable numericdisplay devices 162 of the 7-segment incandescent type, therebyproviding the digital display 14 illustrated in FIG. 1.

The modified circuitry illustrated in FIG. 5 is a substitute for thecalibration oscillator 52. The output of the time base oscillator 30 inthis instance provides a reference frequency and is fed to one input ofa phase detector 170. The error signal output of the phase detector 170is fed to a voltage controlled oscillator 172 having an output connectedto a programmable frequency divider 174 and a divde-by-Z network 176.The output of the frequency divider 174 is connected to the other inputof the phase detector 170 to provide a phaselocked loop. Programmingswitches 178 for the frequency divider 174 are set to the number P, aparameter to be discussed under the next heading hereinafter. A codednumber equal to the number P is obtainable at the programming switches178 as indicated. The output replacing the output of the calibrationoscillator 52 of FIG. 4a is taken at the output of the divde-by-2network 176, as represented by the lead 180.

The modification of FIG. 6 eliminates the calibration oscillatoraltogether and employs a high frequency time base oscillator 200 have a50 KHz output. A divide-by- 500 network 202 then provides the time basefrequency of 100 Hz. The output of the oscillator 200 is fed to oneinput of a Z-input AND gate 204, the other input thereof being connectedto the output of a gate pulse generator 206 corresponding to the Qoutput of the flip-flop 104 in FIG. 4a. The output of the AND gate 204is fed to an adder 208 that has its output connected to an accumulatingregister 210 corresponding to the up-counter 140 in FIG. 4a. The adder208 is set in accordance with the number P through the use ofprogramming switches 212, a coded number equal to P being obtainableatthe programming switches 212 as indicated.

THE SPEED COMPUTATION EQUATION In the discussion under this heading andsubsequent headings, it will be assumed for purposes of illustrationthat all computations are based on vehicle performance and operationover a distance of one quarter mile. It will be understood, of course,that the quarter mile distance is entirely arbitrary from acomputational standpoint but is, in fact, useful from a practicalstandpoint in that, in the case of elapsed time from a standing start inthe drag racing field, quarter mile performance is commonly the distanceof interest.

If the number of wheel revolutions per quarter mile for a particularvehicle is N, and the period of a wheel revolution at some speed ismeasured at t in seconds, then speed, in miles per hour 900/! N.

In the present invention, two pulses are generated for each wheelrevolution by virtue of the two diametrically opposed magnets 20 on therim of the wheel 18. Accordingly,

where P is equal to the number of pulses per quarter mile. Furthermore,it is desired that the computer have sufficient resolution to displayspeed in terms of tenths of miles per hour. Therefore, multiplying thenumerator of the above speed equation by a factor of 1,000 andmultiplying the denominator by a factor of 100, the result is speed, intenths of miles per hour 900,000/50 t P.

This speed equation is implemented in the circuitry of FIG. 4a of thepresent invention by adjusting the cal ibration oscillator 52 to afrequency of SOP Hz and then gating the oscillator output with a pulseof width 1, which is equal to the period of one wheel revolution. Aswill be discussed hereinafter, the pulse of width 1 appears at the Qoutput of the flip-flop 104. The resultant number thus obtained isdivided into the fixed number 900,000, the quotient being speed intenths of miles per hour.

OPERATION IN SPEEDOMETER MODE Beginning from the left, the first fourpush buttons of the row of selector buttons 16 in FIG. 1 are connectedto a mechanical interlock (not shown) so that normally only one of thesebuttons will be depressed at a time. Assuming that the operator wishesfor the computer to continuously display the speed of the vehicle, theSP button is depressed to close the switch 108 (FIG. 4a)

and to actuate the mode switch 156 (FIG. 4b) thereby connecting theoutput of the counter 62 to the decoder 160. Since the flip-flop 96 isactivated by the presence of a low logic level at any of its inputs, theflip-flop 96 is set by the closure of the switch 108.- This causes itsoutput along lead 102 to change to the high logic level therebyreleasing the flip-flops 104 and 106 for continuous operation. At thesame time, one of the inputs of the NAND gate 112 is held at the lowlogic level via lead 110, thus the output of NAND gate 112 will be atthe high logic level and remain at such level so that the wheel pulsesfrom the Schmitt trigger 82 will pass through the NAND gate 84 and becontinuously applied to the clock inputs of the flip-flops 104 and 106.

Assuming for purposes of illustration that the Q outputs of both of theflip-flops 104 and 106 are at the high logic level, the next wheel pulsereaching the clock in puts causes the Q output of the flip-flop 106 togo low (Q high) while the Q output of the flip-flop 104 remains high. 0nthe next succeeding wheel pulse, both Q outputs go low. The next wheelpulse causes both Q outputs to return to the high logic level, and thecycle repeats. Accordingly, it may be appreciated that the Q output ofthe flip-flop 104 is high for twice as long as it is low. The timeduration at the high logic level is equal to t (the period of one wheelrevolution) and the time duration at the low logic level is thus equalto t/2. This is illustrated in FIG 4a by the wave form 220.

As mentioned previously, the calibration oscillator is at a frequencyequal to SOP Hz, where P is the number of wheel pulses produced by thevehicle in traveling a quarter mile. The NAND gate 58 effects the gatingfunction that, in effect, produces a series of pulses representing thedenominator in the speed equation discussed hereinabove. The wave form222 in FIG. 4a represents the output of the NAND gate 58 during the timet of the wave form 220. The wave form 222 comprises a series of speedinformation signals in the nature of counting pulses equal in number to50 t P.

The operation of the apparatus in the speedometer mode is furtherunderstood with reference to FIG. 8. The first or top graph of thetiming diagram illustrates the wheel pulses fromthe Schmitt trigger 82.The second graph illustrates that the lead 102 is maintained at the highlogic level. The third graph shows the output of the NAND gate 84, whichis the inverse of the wheel pulses. The fourth graph shows the 6 outputof the flipfiop 106. The fifth and sixth graphs illustrate the Q and 6outputs respectively of the flip-flop 104. The seventh graph depicts theoutput of the NAND gate 146. The eighth graph shows the series ofcountingpulses delivered at the output of the NAND gate 58. The ninthgraph shows the output of the NAND gate 118. The tenth graph shows theoutput of the NAND gate 154. Graph No. 11 shows the end of computationpulse delivered by the adder 142. Graphs 12 and 13 illustrate theoutputs of flip-flop 122 and the clock 132 respectively.

The series of counting pulses from the output of the NAND gate 58 arefed to the up-counter 140. The output of the NAND gate 118 goes low withthe occurrence of the wheel pulse whose trailing edge is at thetermination of the time t. This triggers the flip-flop 122 to, in turn,reset the adder 142 and place one of the inputs of the AND gate 128 atthe high logic level. Shortly thereafter, when the Q output of flip-flop104 goes high, the AND gate 128 triggers the clock 132 to initiateoperation of the computation section 134 of the computer apparatus. Atthis time, division is performed pursuant to the speed equationdiscussed above. The augend/sum register 139 stores the complement of900,000 and is preset to such complement when the output of the NANDgate 118 goes low. During operation of the clock 132, the number storedin counter 140 (the number of counting pulses received from the NANDgate 58) is repeatedly added to such complement until the register 139fills. The computation then stops and the end computation signal isproduced by .the adder 142 to reset the flip-flop 122. During thecomputation, a pulse is produced by the adder 142 and delivered at thequotient lead 150 each time the number in counter 140 is added to thecomplement in register 139. These quotient pulses are accumulated in thespeed register 152. Except during the actual computation period when thedisplay devices 162 are blanked, the count accumulated in the speedregister 152 is continuously indicated by the display devices 162.Accordingly, the computation section 134 accumulates counting pulsesduring a wheel revolution, effects the speed computation at the outsetof the following half revolution, and then repeats the cycle so that thespeedometer display is updated every one and one-half revolutions of thewheel. It should be understood that the time that the display devices162are blanked is sufficiently short to be undetectable by the eye atnormal road speeds and above.

OPERATION IN ELAPSED TIME MODE Selection of the elapsed time mode by theoperator is made by pressing the ET button in the row of buttons 16(FIG. 1). In FIG. 4b this function is illustrated schematically by themode switch 156 which, in the elapsed time mode, connects the output ofthe elapsed time counter 78 directly to the input of the decoder 160.

With the vehicle stopped the operator first presses the reset button(RES in FIG. 1) to effect momentary closure of the reset switch 44. Thelow logic level reset pulse 46 thus produced resets the up/down counter62 and the elapsed time counter 78. The speed register 152 is also resetso that terminal speed information may also ultimately be obtained, aswill be discussed under a subsequent heading. Furthermore, theflip-flops 32 and 34 are reset so that they are now responsive to thetiming signals from the time base oscillator 30 appearing at the clockinputs C.

After being reset, the first pulse from the time base oscillator 30causes the Q output of the flip-flop 32 to change to the high logiclevel, while the Q output of the flip-flop 34 remains at the log logiclevel. The second pulse from the time base oscillator 30 causes the Qoutput of the flip-flop 34 to change to the high logic level, withoutchanging the level of the Q output of the flipflop 32. The third pulsefrom the oscillator 30 causes the Q output of the flip-flop 32 to go tothe low level, and thereafter subsequent pulses have no effect on theflip-flops 32 and 34 until such time that they are once again reset.Accordingly, the wave form 223 illustrates the output characteristic ofthe Q output of the flip-flop 32, which is at the high logic level for atime duration commencing with the trailing edge of the first pulse fromthe oscillator 30 and ending with the trailing edge of the third pulsefrom the oscillator 30. This time duration is equal to 20 millisecondsand is used to gate the output of the calibration oscillator 52 via theNAND gate 42 so that the output of the NAND gate 42 is a series ofpulses equal to the number P. It will be recalled that P is equal to thenumber of pulses produced by the wheel 18 as it traverses a quartermile. Since the frequency of the calibration oscillator 52 is SOP Hz,the 20 milliseconds gate causes P pulses to be delivered at the outputof the NAND gate 42. These pulses are fed directly to the up-countinginput of the up/down counter 62 to preset the number P into theregister.

Having reset the apparatus, the operator may then commence the run. Asthe wheel 18 revolves, wheel pulses are. fed to the down-counting inputof the counter 62 to reduce the stored count. When the count reacheszero, the vehicle has traveled a quarter mile and an output commandpulse 224 appears at the borrow output 64. This resets the flip-flop 66which was previously set at the beginning of the run by the closing ofthe mercury switch 74. At the time that the flip-flop 66 was set, itsoutput went high to enable the NAND gate 38 and permit the timingsignals from the oscillator 30 to be received by the elapsed timecounter 78. Resetting of the flip-flop 66 by the output command pulse224 disables the gate 38 to, in turn, terminate operation of the counter78. Accordingly, the display 162 (in one hundredths of a second) holdsthe elapsed time figure for the quarter mile.

OPERATION IN TERMINAL SPEED MODE The output command pulse 224 justreferred to above also sets the flip-flop 96. Having been reset duringthe quarter mile run, the flip-flops 104 and E06 were not permitted torespond to the wheel pulses. However, setting of the flip-flop 96releases the flipflops 104 and 106 so that the speed of the vehicle willbe computed on the next revolution ofthe wheel 18. The computationproceeds as in the speedometer mode but for one wheel revolution only,the result being held in the speed register 152 where it may beselectively switched to the display devices 162 by operation of the modeswitch 156 (pressing the TS button illustrated in FIG. 1).

FIG. 7 is similar to FIG. 8 but illustrates computer operation in theelapsed time or terminal speed mode. The various graphs are numbered tocoincide with FIG. 8, two additional graphs being added between Nos. 1and 2 to illustrate the reset function and the end of quarter command,which is the output command pulse 224 from the up-down counter 62. Thefirst segment of the timing diagram depicts the condition of the systemduring staging (vehicle stopped in preparation for running the quarter).Here it may be noted that the reset pulse 46 occurs as discussed above.The second segment of the timing diagram depicts the running of thevehicle through the quarter. The third segment of the diagram shows theoperation at the end of the quarter, where the command pulse 224 isseen. Note that once the O outputs of both of the flip-flops 104 and 106are at the high logic level, the flip-flops 104 and 106 do not changestate as subsequent wheel pulses are produced. Referring to FIG. 4a,this is because the lead 110 is at the high logic level since thespeedometer mode switch 108 is open. Thus, when all three of the inputsof the NAND gate 112 are high, its output goes low and remains at thelow level to disable the following NAND gate 84, thereby preventingsubsequent wheel pulses from reaching the clock inputs of the flip-flops104 and 106. Accordingly, only one speed computation is made.

OPERATION IN CALIBRATE MODE The number of pulses P per quarter mile willvary with each vehicle in accordance with tire sizes and other factors.Accordingly, to calibrate the apparatus the operator actuates the modeswitch 156 to cause the output of the up/down counter 62 to be feed tothe display devices 162. The 3-pole calibrate switch 88 is also actuatedso that wheel pulses will now be fed to the upcounting input of thecounter 62. No push button in the row 16 is illustrated for thisfunction in order to minimize the number of buttons. Mechanically, thefunction may be accomplished through linkage which activates the modeswitch 156 and calibrate switch 88 when the TS and ET buttons aresimultaneously depressed.

To calibrate, the operator stops the vehicle at the beginning of ameasured course, presses the CL button to momentarily close the switch92 and clear the counter 62, actuates the calibrate switch $8 and themode switch 156 to the calibrate mode, and then drives the vehicle overthe measured course. Once the driver has finished the course, thedisplay devices 162 are read to determine the number of pulses that haveoccurred. Assuming that such course is a quarter mile in length thereadout gives the number of pulses P directly. Having brought thevehicle to a stop at the end of the measured course for calibrationpurposes, the operator may then momentarily close the reset switch 44and read from the display devices 162 the number P to which thecalibration oscillator 52 is presently set. The output of the inverteris normally at the high logic level, thus the NAND gate 60 is capable oftransmitting the gated calibration oscillator output on to theup-counting input of the counter 62. If these two numbers are not thesame, the calibration oscillator 52 is adjusted until the numberdisplayed is equal to the number I determined during the calibrationrun. Changing the oscillator frequency may be easily accomplished byproviding a screwdriver adjustment (not shown) accessible from the frontof the unit. The apparatus is now properly calibrated for both elapsedtime and speed computations.

OPERATION FIGS. 5 AND 6 In FIG. 5 the programming switches 178 are setto the number P in binary coded decimal form. The frequency divider 174may, for example, comprise a counter programmable by a binary code and,in this instance, programmed by the switches 178 to divided by thenumber P. The voltage controlled oscillator 172 will, accordingly, bephase locked at a frequency of IOOP Hz, since the phase detector 170will deliver an error signal at its output whenever its two inputs arenot in phase. The out-of-phase condition occurs when the output of theoscillator 172 is other than lOOP Hz, since under this condition thesignal delivered at the output of the frequency divider 174 has afrequency other than Hz. The desired output, of course, is a signalhaving a frequency of SOP Hz, this being obtained at the output of thedivide-by-2 network 176 and fed directly to the NAND gate 58 shown inFIG. 4a. The function of the NAND gate 42 is eliminated since the numberP is now available from the programming switches 178 in parallel formrather than serial form, thus the up/down counter 62 would be directlypreset to the number P just after the apparatus is reset.

In FIG. 6 the timing signals are obtained from the output of thedivide-by-500 network 202, the output of the 50 KHz oscillator 200 beinggated by a pulse of width t. Accordingly, the output of the AND gate 204is a series of pulses equal in number to 50,000t. The programmingswitches 212 are set to the number P in binary coded decimal form. Sincethe number of pulses appearing at the output of the AND gate 204 and fedto the adder control input is a thousand times the number needed toeffect the speed equation discussed above, the adder 208 adds 0.001P tothe register 210 each time it receives a pulse at its control input.Accordingly, the register 210 receives a series of speed informationsignals from the adder 208 and ultimately accumulates a number equal to50 t P, the same as the up-counter in FIG. 4a. Again, P is available inparallel form to preset the up/down counter 62.

Having thus described the invention, what is claimed as new and desiredto be secured by Letters Patent is: 1. Apparatus for computing the timerequired for a vehicle to travel over a course of predetermined lengthand the terminal speed thereof, said apparatus comprisa time baseoscillator for producing a series of timing signals occurring atpredetermined time intervals; an elapsed time counter for receiving saidsignals; means responsive to movement of said vehicle for producing atrain of pulses, the number of which is indicative of the distancetraveled by the vehicle Elli and which occur at intervals dependent uponthe speed of the vehicle; control means operably associated with saidcounter and said movement responsive means for rendering the counteroperational at the outset of said course, whereby said timing signalsare received and counted by the counter, and for terminating operationof the counter when the number of said pulses thereafter occurringcorresponds to the length of said course; and speed computing meanscoupled with said control means for determining the terminal speed ofthe vehicle when said number of pulses occurs corresponding to thelength of said course. 2. The apparatus as claimed in claim 1, saidcontrol means including means responsive to said pulses for counting thelatter and for delivering an output command to effect said terminationof counter operation when the number of pulses counted corresponds tothe length of said course. 3. The apparatus as claimed in claim 2, saidcontrol means further including gating means for effecting delivery ofsaid timing signals to said elapsed time counter at the outset of saidcourse, said gating means terminating delivery of said signals inresponse to said command. 4. The apparatus as claimed in claim 1, saidcontrol means including a pulse counter, count presetting means operableprior to operation of said elapsed time counter for causing the pulsecounter to store a number representing the number of said pulsescorresponding to the length of said course, and means for deliveringsaid pulses to said pulse counter to cause the latter to count from saidstored number, said pulse counter delivering an output command to effectsaid termination of operation of the elapsed time counter after countingto a state eliminating said stored number. 5. The apparatus as claimedin claim 4, said control means further including gating means foreffecting delivery of said timing signals to said elapsed time counterat the outset of said course, said gating means terminating delivery ofsaid signals in response to said command. 7 6. The apparatus as claimedin claim 1, said movement responsive means including a pickup device forsensing the rotation of an undriven wheel of said vehicle, and meansresponsive to said device for delivering a constant number of saidpulses during each revolution of said wheel. 7. The apparatus as claimedin claim ll, there being readout means for displaying time and speedinformation; and switching means coupled with said counter, said speedcomputing means, and said readout means for selectively connecting theoutputs of the counter and the speed computing means with the readoutmeans. 8. Apparatus for computing the speed of a moving vehicle at theend of a course of predetermined length, said apparatus comprising:

first means responsive to rotation of a wheel of said vehicle forproducing a train of wheel pulses which have a repetition rateindicative of the period of a wheel revolution;

second means responsive to said wheel pulses for deriving a series ofspeed information signals having a time duration from the beginning tothe end of said series governed by the interval between a pair of saidwheel pulses,

said signals having a characteristic indicative of the number of saidwheel pulses that occur when the vehicle travels a predetermineddistance,

said second means having control means for providing a gate pulse equalin duration to said interval, and means responsive to said gate pulsefor delivering said series of speed information signals;

output means coupled with said control means for indicating the speed ofthe vehicle upon delivery of said signals thereto;

computing means coupled with said first means and responsive to saidwheel pulses for determining the instant that the vehicle finishestraveling over said course; and

means responsive to said computing means and coupled with said controlmeans for activating the latter to provide said gate pulse as thevehicle finishes said course, whereby said output means indicates theterminal speed of the vehicle.

9. A method of computing the time consumed by a vehicle in travelingover a course of predetermined length and the terminal speed thereof,said method comprising the steps of:

producing a series of timing signals occurring at predetermined timeintervals;

producing a train of pulses in response to movement of the vehicle, thenumber of which is indicatve of the distance traveled by the vehicle andwhich occur at intervals dependent upon the speed of the vehicle;

counting said timing signals beginning at the outset of said course anduntil the number of said pulses thereafter occurring corresponds to thelength of said course; and

at the end of said course, deriving the speed of the vehicle from theinterval between a pair of said pulses then occurring and said number ofpulses corresponding to the length of the course, whereby to computeboth the elapsed time in traveling the course and the terminal speed.

10. A method of computing the speed of a moving vehicle at the end of acourse of predetermined length, said method comprising the steps of:

producing a train of wheel pulses in response to rotation of a wheel ofsaid vehicle, said pulses having a repetition rate indicative of theperiod of a wheel revolution; I 1

determining in response to said wheel pulses the instant that thevehicle finishes traveling over said course; delivering a series ofspeed information signals at said instant having a time duration fromthe beginning to the end of said series governed by the interval betweena pair of said wheel pulses then occurring,

said signals having a characteristic indicative of the number of saidwheel pulses that occur when the vehicle travels a predetermineddistance; and

mathematically processing said series of signals to derive the terminalspeed of the vehicle.

11. The method as claimed in claim 10,

said processing of said series of signals including deriving therefrom anumber representing the time required for the vehicle to travel saiddistance, and dividing the last mentioned number into a fixed numberhaving a value depending upon the expression desired for the quotient.

12. Apparatus for computing the time required for a vehicle to travelover a course of predetermined length, said apparatus comprising:

a time base oscillator for producing a series of timing signalsoccurring at predetermined time intervals; an elapsed time counter forreceiving said signals; means responsive to movement of said vehicle forproducing a train of pulses, the number of which is indicative of thedistance traveled by the vehicle and which occur at intervals dependentupon the speed of the vehicle; control means operably associated withsaid counter and said movement responsive means for rendering thecounter operational at the outset of said course, whereby said timingsignals are received and counted by the counter, and for terminatingoperation of the counter when the number of said pulses thereafteroccurring corresponds to the length of said course, said control meansincluding a pulse counter, count presetting means operable prior tooperation of said elapsed time counter for causing the pulse counter tostore a number representing the number of said pulses corresponding tothe length of said course, and means for delivering said pulses to saidpulse counter to cause the latter to count from said stored number,

said pulse counter delivering an output command to effect saidtermination of operation of the elapsed time counter after counting to astate eliminating said stored number;

a calibration switch operable to effect delivery of said pulses to saidpulse counter to cause the latter to count from zero as the vehicletravels said course; and

means responsive to said pulse counter for displaying the number countedduring calibration operation,

said count presetting means being selectively operable to set the countstored by said pulse counter prior to timing a run over said course at avalue corresponding to the number displayed during calibration operationafter traveling said course. III

1. Apparatus for computing the time required for a vehicle to travel over a course of predetermined length and the terminal speed thereof, said apparatus comprising: a time base oscillator for producing a series of timing signals occurring at predetermined time intervals; an elapsed time counter for receiving said signals; means responsive to movement of said vehicle for producing a train of pulses, the number of which is indicative of the distance traveled by the vehicle and which occur at intervals dependent upon the speed of the vehicle; control means operably associated with said counter and said movement responsive means for rendering the counter operational at the outset of said course, whereby said timing signals are received and counted by the counter, and for terminating operation of the counter when the number of said pulses thereafter occurring corresponds to the length of said course; and speed computing means coupled with said control means for determining the terminal speed of the vehicle when said number of pulses occurs corresponding to the length of said course.
 2. The apparatus as claimed in claim 1, said control means including means responsive to said pulses for counting the latter and for delivering an output command to effect said termination of counter operation when the number of pulses counted corresponds to the length of said course.
 3. The apparatus as claimed in claim 2, said control means further including gating means for effecting delivery of said timing signals to said elapsed time counter at the outset of said course, said gating means terminating delivery of said signals in response to said command.
 4. The apparatus as claimed in claim 1, said control means including a pulse counter, count presetting means operable prior to operation of said elapsed time counter for causing the pulse counter to store a number representing the number of said pulses corresponding to the length of said course, and means for delivering said pulses to said pulse counter to cause the latter to count from said stored number, said pulse counter delivering an output command to effect said termination of operation of the elapsed time counter after counting to a state eliminating said stored number.
 5. The apparatus as claimed in claim 4, said control means further including gating means for effecting delivery of said timing signals to said elapsed time counter at the outset of said course, said gating means terminating delivery of said signals in response to said command.
 6. The apparatus as claimed in claim 1, said movement responsive means including a pickup device for sensing the rotation of an undriven wheel of said vehicle, and means responsive to said device for delivering a constant number of said pulses during each revolution of said wheel.
 7. The apparatus as claimed in claim 1, there being readout means for displaying time and speed information; and switching means coupled with said counter, said speed computing means, and said readout means for selectively connecting the outputs of the counter and the speed computing means with the readout means.
 8. Apparatus for computing the speed of a moving vehicle at the end of a course of predetermined length, said apparatus comprising: first means responsive to rotation of a wheel of said vehicle for producing a train of wheel pulses which have a repetition rate Indicative of the period of a wheel revolution; second means responsive to said wheel pulses for deriving a series of speed information signals having a time duration from the beginning to the end of said series governed by the interval between a pair of said wheel pulses, said signals having a characteristic indicative of the number of said wheel pulses that occur when the vehicle travels a predetermined distance, said second means having control means for providing a gate pulse equal in duration to said interval, and means responsive to said gate pulse for delivering said series of speed information signals; output means coupled with said control means for indicating the speed of the vehicle upon delivery of said signals thereto; computing means coupled with said first means and responsive to said wheel pulses for determining the instant that the vehicle finishes traveling over said course; and means responsive to said computing means and coupled with said control means for activating the latter to provide said gate pulse as the vehicle finishes said course, whereby said output means indicates the terminal speed of the vehicle.
 9. A method of computing the time consumed by a vehicle in traveling over a course of predetermined length and the terminal speed thereof, said method comprising the steps of: producing a series of timing signals occurring at predetermined time intervals; producing a train of pulses in response to movement of the vehicle, the number of which is indicatve of the distance traveled by the vehicle and which occur at intervals dependent upon the speed of the vehicle; counting said timing signals beginning at the outset of said course and until the number of said pulses thereafter occurring corresponds to the length of said course; and at the end of said course, deriving the speed of the vehicle from the interval between a pair of said pulses then occurring and said number of pulses corresponding to the length of the course, whereby to compute both the elapsed time in traveling the course and the terminal speed.
 10. A method of computing the speed of a moving vehicle at the end of a course of predetermined length, said method comprising the steps of: producing a train of wheel pulses in response to rotation of a wheel of said vehicle, said pulses having a repetition rate indicative of the period of a wheel revolution; determining in response to said wheel pulses the instant that the vehicle finishes traveling over said course; delivering a series of speed information signals at said instant having a time duration from the beginning to the end of said series governed by the interval between a pair of said wheel pulses then occurring, said signals having a characteristic indicative of the number of said wheel pulses that occur when the vehicle travels a predetermined distance; and mathematically processing said series of signals to derive the terminal speed of the vehicle.
 11. The method as claimed in claim 10, said processing of said series of signals including deriving therefrom a number representing the time required for the vehicle to travel said distance, and dividing the last mentioned number into a fixed number having a value depending upon the expression desired for the quotient.
 12. Apparatus for computing the time required for a vehicle to travel over a course of predetermined length, said apparatus comprising: a time base oscillator for producing a series of timing signals occurring at predetermined time intervals; an elapsed time counter for receiving said signals; means responsive to movement of said vehicle for producing a train of pulses, the number of which is indicative of the distance traveled by the vehicle and which occur at intervals dependent upon the speed of the vehicle; control means operably associated with said counter and said movement responsive means for rendering the counter operational at the outset of said course, whereBy said timing signals are received and counted by the counter, and for terminating operation of the counter when the number of said pulses thereafter occurring corresponds to the length of said course, said control means including a pulse counter, count presetting means operable prior to operation of said elapsed time counter for causing the pulse counter to store a number representing the number of said pulses corresponding to the length of said course, and means for delivering said pulses to said pulse counter to cause the latter to count from said stored number, said pulse counter delivering an output command to effect said termination of operation of the elapsed time counter after counting to a state eliminating said stored number; a calibration switch operable to effect delivery of said pulses to said pulse counter to cause the latter to count from zero as the vehicle travels said course; and means responsive to said pulse counter for displaying the number counted during calibration operation, said count presetting means being selectively operable to set the count stored by said pulse counter prior to timing a run over said course at a value corresponding to the number displayed during calibration operation after traveling said course. 